1. Field of the Invention
The present invention relates to an instruction cache memory with advance read function positioned between a processing device such as microprocessor and a main memory, for buffering the difference in the operating speed of the two, and more particularly to an improvement of its hit rate.
2. Description of the Background Art
In an ordinary processor, the memory layers are composed of several levels. The control of such memory layers is effected in the unit of every two adjacent levels.
Referring to FIG. 25, a memory device 200 closer to the CPU 18 is called a caches, and the remoter memory device is a memory 22. At these two levels, the minimum unit of data subject to memory control is called a block. Data giving and receiving between cache and memory is effected in the block unit.
The CPU 18 sends an access request composed of control signal (load/store) and address, to the cache 200. The cache 200, when holding inside the data of the address indicated by the access request, promptly outputs data to the CPU 18, and when not holding and the access to the cache is a failure, it sends a read request composed of control signal (load/store) and address to the memory 22, and the data of the address indicated by the read request is fetched from the memory 22, and transferred to the CPU 18.
A failure of access to the cache (the objective data not found in the cache) is called an error. The error rate is the rate of access failure. The hit rate is an inverse number of the error rate, and means the successful access rate. The error penalty refers to the sum of the time for replacing the block in the cache 200 by the block transferred from the memory 22, and the time for sending the data to the CPU 18 outputting the access request to the block.
Generally, the CPU time showing the processor performance is given in the following formula.
CPU time=number of execution instructions.times.(number of clocks per instruction (CPI)+average number of errors per instruction.times.error penalty).times.clock cycle time
As known from this formula, even in the same CPU, the performance varies with the cache behavior. In the CPU with low CPI and high clock frequency, lowering of performance due to cache error is more serious. This is because the rate of effect of cache error increases as the CPI value is smaller.
Or, if the CPU is different, the memory chips used in the main memory are often of the same kind. Therefore, regarding the main memory access time alone, there is almost no difference among computers. The error penalty is expressed as the value of the time necessary for processing the error represented by the number of CPU clocks. If the access time of the main memory is same, the error penalty value increases as the number of clocks of CPU becomes higher. Accordingly, in the CPU with high clock frequency, lowering of performance due to cache error is more serious.
It is thus known that the cache error has a large effect on the performance of the processor. That is, the probability of occurrence of errors has a large importance on the system performance.
The cache memory may be divided into the instruction (exclusive) cache and data (exclusive) cache. By using independent caches for the instruction and data, a constitution optimum for handling of instruction and data can be set up, and hence it is advantageous for enhancement of performance of the entire system. In particular, in the instruction cache memory, by more deeply studying the mode of execution of a series of instructions, there is a possibility of further optimizing the operation of the instruction cache memory.